Semiconductor integrated circuit device and method of manufacturing the same, and cell size calculation method for DRAM memory cells

ABSTRACT

There is provided a semiconductor integrated circuit device comprising: a field placement creating a field pattern in an array form by closest packing on a first conductance-type semiconductor substrate, the field pattern including a plurality of memory cells which define an active area and a device isolation region of a field effect transistor, and which are arranged in a predetermined pitch in the longitudinal and transverse directions, respectively, each memory cell having a pattern of a certain length-to-width size; a cell plate placement providing a capacitor structure between a second conductance-type diffusion region formed by an impurity implant to the active area and a cell plate electrode formed so as to cover part of the active area with a predetermined cell plate pattern through a capacitor dielectric, the cell plate pattern extending in the transverse direction with a certain length size; and a word line placement in which a word line pattern is arranged in the transverse direction of a vacant zone of the active area in which the cell plate electrode is not formed and serves as a gate electrode of the field effect transistor on the active area, the word line pattern being formed through a gate oxide at a predetermined interval, wherein the layout of a cell array of the memory cells is provided by a closest packing cell configuration.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor integratedcircuit device such as a system LSI incorporating DRAMs, a method ofmanufacturing the same, and a cell size calculation method for DRAMmemory cells.

[0003] 2. Description of the Prior Art

[0004] In recent years, a DRAM mixing or hybrid system LSI whichintegrates a logic such as processor, ASIC, or the like, and alarge-scale DRAM on a common semiconductor substrate has been appliedfor many purposes. In such a system LSI, an internal data bus ofmultiple bits, e.g. 128-512 bits, makes an interconnection between thelogic and the DRAM, thus achieving a data transmission speed which ishigher by one to two orders, as compared to a case that a commerciallyavailable DRAM and a logic each having a small number of terminals areconnected with each other on a common printed circuit board.

[0005] In addition, with respect to the logic, the number of externalinput pins may be reduced as compared to a system configuration whichmounts externally the commercially available DRAMs. Further, a DRAMblock is connected to a logic via an internal wiring inside the systemLSI. Since the length of the internal wiring is sufficiently shorterthan that of wirings on the printed circuit board, and also has a smallparasitic impedance, charging and discharging currents can bedrastically reduced, and signal transmissions can be carried out at highspeed.

[0006] From these reasons, the DRAM hybrid system LSI has contributedgreatly to the high performance of intelligence apparatuses that dealwith a large amount of data of 3-D graphic processing, image and voiceprocessing, and the like.

[0007]FIG. 17 is a schematic block diagram illustrating a configurationexample of a conventional semiconductor integrated circuit device, whichdesignates a DRAM mixing or hybrid system LSI. In FIG. 17, referencenumeral 100 designates a power supply pin terminal for feeding powersupply potential exVdd; 101 designates a large scale logic (LG); 102designates an analog core (ACR); 103 designates a DRAM core (MCR); 104designates a test interface circuit (TIC); 105 designates a firstexternal pin terminal group (LPGA); 106 designates a second external pinterminal group (APG); and 107 designates a test pin terminal group(TPG).

[0008] The aforementioned system LSI includes: the large scale logic101, connected to the first external pin terminal group, for executing acommanded processing; the analog core 102, connected between the largescale logic 101 and the second external pin terminal group 106, forexecuting a processing of analog signals; the DRAM core 103, connectedto the large scale logic 101 via internal wirings, for storing datarequired by the large scale logic 101; and a test interface circuit 104for executing a test operation for the DRAM core 103 through the testpin terminal group 107 while separating the large scale logic 101 andthe DRAM upon a test mode. The DRAM core 103 receives a power supplyvoltage exVDD via the power supply pin terminal 100.

[0009] The analog core 102 includes a Phase-Locked Loop (PLL) forgenerating an internal clock signal; an analog/digital (A/D) converterfor converting an externally inputted analog signal to a digital signal;and a digital/analog (D/A) converter for converting a digital signalsupplied from the large scale logic 101 to an analog signal to beoutputted.

[0010]FIG. 18 is a sectional schematic illustration taken along anarbitrary line in a large scale logic unit during a conventionalDRAM-logic mixing process. In FIG. 18, reference numeral 201 designatesa semiconductor substrate; 202 designates a first interlayer dielectric;203 a and 203 b each designate a second interlayer dielectric; 204designates a third interlayer dielectric; 205 designates a fourthinterlayer dielectric; 206 designates a cover film; 211 designates aword line; 221 designates a bit line; 222 designates a first metalwiring; 223 designates a second metal wiring; 224 designates a thirdmetal wiring; 231 designates a via plug such as tungsten W; 241designates a contact hole; 242 designates a first through hole forconnecting the first metal wiring 222 with the second metal wiring 223;and 243 designates a second through hole for connecting the second metalwiring 223 with the third metal wiring 224.

[0011] In FIG. 18, an n-channel or p-channel MOS transistor is firstformed on the semiconductor substrate electrically separated by trenchisolation. The gate electrode is formed by a wiring layer made of asilicon containing material, for example, polysilicon doped with animpurity or doped polysilicon, polycide such as tungsten silicide(WSix), and the like, and serves as the word line 211 through amicrofabrication.

[0012] Metal wiring layers for multilevel metallization are formed by ametal such as aluminum Al or an alloy containing copper Cu therein onthe upper layer of the MOS transistor with interposing the first tofourth interlayer dielectrics 202205. These wiring layers aremicro-fabricated independently to form the first metal wiring 222,second metal wiring 223, and third metal wiring 224.

[0013] These metal wirings 222-224 are electrically connected to thewiring layer of the bit line 221 formed by a material such as tungstenvia the via plug 231 in which tungsten W or the like is buried in thecontact hole 241 and through holes 242 and 243.

[0014] Note that the above-described bit line 221 is not required in aperfect CMOS logic process which mixes no DRAMs.

[0015]FIG. 19 is a schematic diagram of a memory cell array section of aDRAM core in a conventional semiconductor integrated circuit device, andFIG. 20 is a sectional schematic illustration taken along an arbitraryline in the longitudinal direction of the memory cell array of FIG. 19.In FIG. 19, reference numeral 301 designates a cell plate electrode CP;302 designates a storage node contact; 303 designates a bit linecontact; 305 designates a sense amplifier S/A; 310 designates a sub-worddriver range (odd); 311 designates a sub-word driver range (even); 315and 316 designate main word lines MWL<i> and MWL<i+1> (i=naturalnumber), respectively; BL and ZBL designate a non-inversion bit line andan inversion bit line, respectively; and WL designates a word line,which connects with the main word line MWL via the logic gate.

[0016] The memory cell is typically composed of a capacitor for storingan electric charge and a field effect transistor (FET) or MOS transistoroperating as a cell selection switch, and is called one transistor type.The gate electrode of this transistor is connected to the word line WLwhich feeds a selection signal of the memory cell, and controls theopening and closing of the memory cell. On the other hand, the drain ofthe transistor is connected to the bit lines BL and ZBL for cellinformation intake which are wired perpendicularly to the word line WL,and exchanges of data between memory cell and read or write circuit willbe carried out through the drain.

[0017] In FIG. 20, the reference numeral 401 designates a semiconductorsubstrate 401; 402 designates a trench isolation region; 403 designatesa word line; 403 a designates a transistor gate wiring; 405 designates aconfiguration dummy bit line; 406 designates a bit line; 407 designatesa storage node; 408 designates a cell plate electrode CP; 409 a, 409 b,and 411 each designate a contact buried by a via plug made of tungstenW; 410 designates a first metal wiring serving as a main word line; 412designates a second metal wiring serving as a VCP power supply line; 421designates a first interlayer dielectric; 422 a and 422 b each designatea second interlayer dielectric; and 423 designates a third-interlayerdielectric.

[0018] Incidentally, a capacitor dielectric is formed between thestorage node 407 and the cell plate CP 408, and these componentsconstruct a stacked capacitor to store a signal electric charge.

[0019] The operation will be next described below.

[0020] The sense amplifier S/A for amplifying a micro-signal isconnected to each of the bit lines BL and ZBL, and the input/output ofdata to the external is carried out through a multiplexer for selectinga specific bit line out of a plurality of bit lines BL and ZBL. Aflip-flop is normally employed for the sense amplifier S/A, and a pairof bit line signals are inputted as a differential signal. The voltageof a reference signal which pairs with the bit line signal is generatedthrough a dummy cell which is constructed by the same circuit as that ofthe memory cell.

[0021] On reading of the cell data, for example, after the bit line ischanged to one potential, the word line WL to be selected is activatedby a word line driver including the sub-word driver ranges 310 and 311,thus reading the charge stored in the capacitor to the bit line BL,while the reference voltage is given to the bit line ZBL pairing withthe bit line BL. The sense amplifier S/A amplifies a voltage differenceof the micro-signal which is caused by a difference between the bit linevoltage on reading the cell data and the reference voltage, and theresultant is transferred to an output circuit through the multiplexer.

[0022] On the other hand, on writing of the cell data, the word line WLto be selected is activated and turns on or conduct a cell selectiontransistor, and it is carried out by taking in the cell a high or lowpotential level on the bit lines BL and ZBL.

[0023] A method of manufacturing the conventional semiconductorintegrated circuit as shown in FIG. 20 is schematically described below.

[0024] A trench isolation region is first formed in the semiconductorsubstrate 401 to define an active region serving as a transistor region,and a transistor section is created through a plurality of ionimplantation processes involving a resist pattern formation, and theword line 403 is formed on the transistor section. The first interlayerdielectric 421 is deposited on top, and a desired contact hole is openedby a microfabrication including photolithography and etching processes.Then a wiring layer is deposited on top by sputtering and the bit line406 and configuration dummy bit line 405 are formed by themicrofabrication as well.

[0025] Further, the second interlayer dielectric 422 a is deposited onthis topography and then opened by a desired contact hole. The storagenode 407 is formed to be thoroughly in contact with the substrate 401.Further, the cell plate electrode 408 is formed on the storage node 407with sandwiching the capacitor dielectric, finally effecting aconventional stacked capacitor structure.

[0026] Thereafter, the second interlayer dielectric 422 b is formed onthe topography and opened by through holes, and the via plugs made oftungsten W are buried in the through holes to form the contacts 409 aand 409 b. Then, the first metal wiring 410 is formed to electricallycontact these contacts 409 a and 409 b, and finally, the thirdinterlayer dielectric 423 is deposited and the second metal wiring 412is finally formed on top.

[0027] Here, it should be noted that as to the layout of the memory cellof FIG. 19, a length where a minimum pitch length is projected to thecolumn or bit line direction is equal to half of a layout pitch in thecolumn direction of the memory cell. Note that the minimum pitch lengthis found when the bit line contacts are linked with each other in theslant direction. In addition, the bit line pair connecting the senseamplifier has a folded bit line configuration with strong noiseresistance.

[0028] In the above-described cell size calculation method of DRAMmemory cells, when it is designated by a minimum microfabricationdimension or F called feature size in design, a size ratio(length-to-width) is typically approximate to 2:1, and a 8F2 cell having2F in width size and 4F in length size is employed.

[0029] In FIG. 20, an n-channel or p-channel MOS transistor constructinga memory cell transistor and an array control circuit is created on thesemiconductor substrate 401 that is separated electrically by the trenchisolation region 402. The gate electrode is formed by a wiring layermade of a silicon containing material such as doped polysilicon orpolycide, e.g. WSix, which is the same layer as that of the word line403, as well as the gate wiring 403 a.

[0030] On top of this, the bit line 406 and a capacitor structureincluding layers of the storage node 407 and the cell plate 408 areformed. The bit line 406 is formed by a silicon containing material, forexample, doped polysilicon or polycide such as WSix. Further, amulti-level metal wiring layer having the same structure as that of thelogic unit or the first metal wiring 410 and second metal wiring 412 isformed through the contact 411 on the uppermost layer.

[0031] As shown in FIG. 20, a 3-D capacitor structure having such acomplicated three dimensional structure as heightens the storage node isformed when the capacitor area is still larger to ensure the capacitancein the stacked capacitor. In this case, a large step height, however,occurs between the memory array section and the other peripheral circuitsection, which makes it difficult to tight the wiring pitch in the metalwiring layers. For this reason, it is required to reduce drastically theaforementioned step height by introduction of a planarization processbased on CMP (Chemical Mechanical Polishing).

[0032] Since the conventional semiconductor integrated circuit device,method of manufacturing the same, and cell size calculation method ofDRAM memory cells are configured as described above, for example, in theDRAM hybrid system LSI, it is required to add newly a process step offorming wirings and electrodes which construct the capacitor section inthe DRAM core and a planarization process step of reducing the stepdifference caused by the 3-D structure capacitor to normal CMOS logicprocesses. This leads to a large increase of the number of the totalprocess steps, resulting in boosting the general chip cost.

[0033] On the other hand, there is an SRAM as a hybrid memory that canbe formed by way of complete CMOS logic processes, and the SRAM has beenapplied to cache memories, register file memories, and the like withrespect to a conventional processor.

[0034] Since the SRAM eliminates the following items: a refreshoperation, which is necessary for DRAMS, every a refresh period of time;and a complicated memory control related to the refresh such that anaccess to the memory during refreshing must be on standby till the endof the refresh cycle, it is employed as a main memory for simplicity ofthe system configuration in portable information terminals and the likein the middle of serious requests for down sizing.

[0035] However, there is a drastically improved function in the portableinformation terminals, for example, managing even moving picturesrecently, which requires a further large capacity memory.

[0036] That is, the shrinkage of the memory size in DRAMs makes progressin accordance with the development of microfabrication processes; forexample, a cell size of 0.3 μm² has been already achieved in 0.18 μmDRAM processes. On the other hand, the memory cell of the SRAM isconstructed by six transistors together with p-channel and n-channelones; even when the microfabrication processes make progress, theshrinkage of the memory size does not develop as much as that of DRAMsbecause of the restriction of an isolation distance between p-well andn-well; therefore, the memory size of the SRAM in 0.18 μm CMOS logicprocesses is still the extent of 7 μm², which extends to twenty timesthe memory size of DRAMs as it stands.

[0037] As described above, since the chip size of the SRAM cannot helpenlarging drastically in accordance with its large capacity development,which makes it hard extremely to hybridize 4 M (mega) or more SRAMs withlogic circuits.

SUMMARY OF THE INVENTION

[0038] The present invention is implemented to solve the foregoingdrawbacks. It is therefor an object of the present invention to providea semiconductor integrated circuit device and a method of manufacturingthe same, and a cell size calculation method of a DRAM memory cell inwhich the cell size of a DRAM memory cell is not as small as that of atypical DRAM memory cell but smaller sufficiently than that of a SRAMmemory cell, and may be formed through a certain process near a processfor CMOS logics, thus achieving a mixing memory capable of even a largecapacity which is difficult for SRAMs.

[0039] A semiconductor integrated circuit device according to thepresent invention has the following characteristics:

[0040] Since the cell size of a DRAM memory cell is configured to be notas small as the typical memory cell size but smaller sufficiently thanthat of the SRAM in order to ensure a capacitor capacitance required forDRAM operations, a sufficiently large capacitor area is obtained even ina planar-type capacitor structure, and further a cell plate may beformed in the same layer as that of a word line serving as a gateelectrode of a memory cell transistor; and

[0041] furthermore, since a storage node for the capacitor is formed bya diffusion region on a semiconductor substrate, a step height may beeliminated completely between a memory cell array section and aperipheral circuit section.

[0042] According to a first aspect of the present invention, there isprovided a semiconductor integrated circuit device comprising: a fieldplacement creating a field pattern in an array form by closest packingon a first conductance-type semiconductor substrate, the field patternincluding a plurality of memory cells which define an active area and adevice isolation region of a field effect transistor, and which arearranged in a predetermined pitch in the longitudinal and transversedirections, respectively, each memory cell having a pattern of a certainlength-to-width size;

[0043] a cell plate placement providing a capacitor structure between asecond conductance-type diffusion region formed by an impurity implantto the active area and a cell plate electrode formed so as to cover partof the active area with a predetermined cell plate pattern through acapacitor dielectric, the cell plate pattern extending in the transversedirection with a certain length size; and

[0044] a word line placement in which a word line pattern is arranged inthe transverse direction of a vacant zone of the active area in whichthe cell plate electrode is not formed and serves as a gate electrode ofthe field effect transistor on the active area, the word line patternbeing formed through a gate oxide at a predetermined interval,

[0045] wherein the layout of a cell array of the memory cells isprovided by a closest packing cell configuration.

[0046] Here, the pitch of the memory cell in the transverse directionmay be loosened and at least two bit lines may be arranged for eachpitch of the memory cell in the longitudinal direction.

[0047] The thickness of the capacitor dielectric may be the same as thatof the gate oxide.

[0048] The capacitor dielectric may be made thinner than the gate oxide.

[0049] Another first conductance-type diffusion having a highly dopeddiffusion region may be provided under the diffusion region.

[0050] The capacitor structure may be a trench structure.

[0051] It is preferable that the first conductance-type is p-type andthe second conductance-type is n-type, or the first conductance-type isn-type and that the second conductance-type is p-type.

[0052] According to a second aspect of the present invention, there isprovided a method of manufacturing a semiconductor integrated circuitdevice comprising:

[0053] a first step of forming an active area and a device isolationregion on the main surface of a semiconductor substrate and creating afield pattern of a memory cell array having a plurality of memory cells;

[0054] a second step of carrying out an impurity implant on the mainsurface to form a first conductance type well region which extends to acertain depth;

[0055] a third step of creating a resist pattern which covers part ofthe active area to form a second conductance-type diffusion region bycarrying out the impurity implant through the resist pattern;

[0056] a fourth step of forming in turn a insulating film and an wiringlayer each having a predetermined thickness after removing the resistpattern;

[0057] a fifth step of etching the wiring layer through a desiredpattern created on the top for a microfabrication to form a gateelectrode of a field effect transistor and a cell plate electrode;

[0058] a sixth step of forming insulating sidewalls to the gateelectrode and the cell plate to form a highly doped diffusion regionwith the second conductance-type through a high-dose ion implant;

[0059] a seventh step of forming a first interlayer dielectric to open acontact hole therein by a microfabrication; and

[0060] a eighth step of forming a metal wiring layer and creating ametal wiring from the wiring layer through a microfabrication.

[0061] Here, the third step may include a step of forming a highly dopeddiffusion region with the first conductance-type extending under thesecond conductance-type diffusion region.

[0062] The second step may include a step of forming another insulatingfilm after formation of the well region and the third step includes astep of removing the another insulating film after formation of thesecond conductance-type diffusion region

[0063] The first step may include a step of forming a trench within asection of the memory cell array.

[0064] It is preferable that the first conductance-type is p-type andthe second conductance-type is n-type, or that the firstconductance-type is n-type and the second conductance-type is p-type.

[0065] According to a third aspect of the present invention, there isprovided a memory size calculation method for DRAM memory cellscharacterized in that a cell size of a planar-type capacitor in a memorycell laid out in accordance with a closest packing cell configuration isfound based on a minimum microfabrication dimension.

[0066] According to a fourth aspect of the present invention, there isprovided a memory size calculation method for DRAM memory cells thatwhen the cell sizes in the transverse and longitudinal directions arerepresented nxF and nyF, respectively, based on a minimummicrofabrication dimension F, and a capacitor area for a signal and acell area are represented Scap and Scell, respectively, respectively,and under the conditions of na≧2.5, nx≧2 (integer), and ny≧2 (integer),the na, nx, and ny values are derived so as to bring the cell area Scellto a minimum based on the following formulae (1) and (2):

Scap=(nxF−F)·(nyF−naF−0.5F)  (1)

Scell=nxF·nyF  (2)

BRIEF DESCRIPTION OF THE DRAWINGS

[0067]FIG. 1 is a layout diagram of a memory cell array of asemiconductor integrated circuit device in accordance with an embodiment1 of the present invention;

[0068]FIG. 2 is a sectional schematic illustration of a memory cell ofthe semiconductor integrated circuit device in accordance with theembodiment 1 of the present invention;

[0069] FIGS. 3A-3D are sectional process diagrams showing a method ofmanufacturing a semiconductor integrated circuit device in accordancewith the embodiment 1 of the present invention;

[0070] FIGS. 3E-3G are sectional process diagrams showing a method ofmanufacturing a semiconductor integrated circuit device in accordancewith the embodiment 1 of the present invention;

[0071] FIGS. 3H-3J are sectional process diagrams showing a method ofmanufacturing a semiconductor integrated circuit device in accordancewith the embodiment 1 of the present invention;

[0072]FIG. 4 is a layout diagram in which the memory cell array of asemiconductor integrated circuit device in accordance with theembodiment 1 of the present invention is applied to a half pitch cellconfiguration;

[0073]FIG. 5 is another illustration of a memory cell configuration;

[0074]FIG. 6 is another illustration of a memory cell configuration;

[0075]FIG. 7 is a table showing calculation results from a cell sizecalculation method of a DRAM memory cell in accordance with theembodiment 1 of the present invention;

[0076]FIG. 8 is a table showing calculation results from the cell sizecalculation method of a DRAM memory cell in accordance with theembodiment 1 of the present invention;

[0077]FIG. 9 is a table showing calculation results from the cell sizecalculation method of a DRAM memory cell in accordance with theembodiment 1 of the present invention;

[0078]FIG. 10 is a schematic cross section of a memory cell of asemiconductor integrated circuit device in accordance with an embodiment2 of the present invention;

[0079] FIGS. 11A-11D are sectional process diagrams showing a method ofmanufacturing a semiconductor integrated circuit device in accordancewith the embodiment 2 of the present invention;

[0080]FIG. 12 is a schematic cross section of a memory cell of asemiconductor integrated circuit device in accordance with an embodiment3 of the present invention;

[0081] FIGS. 13A-13D are sectional process diagrams showing a method ofmanufacturing a semiconductor integrated circuit device in accordancewith the embodiment 3 of the present invention;

[0082]FIG. 14 is a schematic cross section of a memory cell of asemiconductor integrated circuit device in accordance with an embodiment4 of the present invention;

[0083]FIG. 15 is a schematic cross section of a memory cell of asemiconductor integrated circuit device in accordance with an embodiment5 of the present invention;

[0084] FIGS. 16A-16D are sectional process diagrams showing a method ofmanufacturing a semiconductor integrated circuit device in accordancewith the embodiment 5 of the present invention;

[0085] FIGS. 16E-16G are sectional process diagrams showing the methodof manufacturing a semiconductor integrated circuit device in accordancewith the embodiment 5 of the present invention;

[0086]FIG. 17 is a schematic block diagram illustrating a configurationexample of a conventional DRAM mixing system LSI;

[0087]FIG. 18 is a sectional schematic illustration of a large scalelogic in a conventional DRAM-logic mixing process

[0088]FIG. 19 is a schematic circuit diagram of a memory cell arraysection in a conventional DRAM core; and

[0089]FIG. 20 is a schematic cross section of the memory cell arraysection in the conventional DRAM core.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0090] An embodiment of the present invention will be described below.

[0091] Embodiment 1

[0092]FIG. 1 is a layout diagram showing schematically the configurationof a memory cell array in a semiconductor integrated circuit device inaccordance with an embodiment 1 of the present invention, and FIG. 2 isa sectional schematic illustration taken along an arbitrary longitudinalline passing a bit line contact BC of FIG. 1.

[0093] In FIGS. 1 and 2, reference symbol BC denotes a bit line contact;WL denotes a word line; BL denotes a non-inversion bit line; ZBL denotesan inversion bit line; CP denotes a cell plate electrode; and S/Adenotes a sense amplifier. Reference numeral 1 designates asemiconductor substrate such as silicon; 2 designates a p-type well(including the channel-cut under the isolation region); 3 designates adevice isolation region; 4 designates a n-type impurity region for aplanar capacitor; 31 designates a gate oxide and a capacitor dielectric;6 designates a gate electrode; 7 designates a cell plate electrode CPfor the planar capacitor; 8 designates a insulating side wall; 9designates an n-impurity region of a transistor; 10 designates ann+impurity region of the transistor; 11 designates a metal salicideformed on the substrate 1; 12 designates a metal salicide formed on thegate electrode 6; 13 designates a first interlayer dielectric; 14designates a bit line contact BC; 15 designates a first barrier metallayer; 16 designates a via plug made of CVD-W for hole burying; 17designates a first aluminum wiring serving as the bit lines BL and ZBL;18 designates a first antireflection film; 19 designates a secondinterlayer dielectric; 20 designates a second barrier metal layer; 21designates a second aluminum wiring; and 22 designates a secondantireflection film for photolithography.

[0094] In FIGS. 1 and 2, a sub-word line (corresponding to theabove-described word line WL) serving as the cell plate electrode CP 7and the gate electrode 6 is formed from the same wiring layer made of asilicon containing material of polycrystalline silicon doped with animpurity such as phosphorus P or doped polysilicon, polycide such asWSix, or the like. In addition, the storage node 407 in the stackedcapacitor shown in FIG. 20 becomes a diffusion layer on thesemiconductor substrate due to the planar capacitor structure.

[0095] The dielectrics under the word line WL and the cell plateelectrode CP 7 are the gate oxide 31 and capacitor dielectric 31 of thememory cell transistor, respectively. Typically, the capacitordielectric 31 is also formed from silicon dioxide; however, these oxideand dielectric may be formed as dioxides each having a differentthickness through a dual-gate-oxide process, or only the capacitordielectric 31 may be formed from a dielectric with a high dielectricconstant such as Ta₂O₅. In addition, the bit lines BL and ZBL has astructure of CUB (Capacitor Under Bit line) which is formed on the upperlayer of the cell plate electrode CP 7.

[0096] It is not required to add newly a wiring layer for the cell plateelectrode CP 7 and storage node 407 (FIG. 20) unlike the prior art, andthe cell plate electrode CP and word line WL are formed from the samewiring layer in the planar-type capacitor structure. Accordingly, thereis no possibility to generate a step height between the memory arraysection and peripheral circuit section. Therefore, without any need ofthe introduction of a planarization process based on CMP and the likefor alleviation of the step height, the memory cell array may be formedthrough processes near the CMOS logic processes.

[0097] The operation will be next described below.

[0098] The sense amplifier S/A for amplifying a micro-signal isconnected to each of the bit lines BL and ZBL, and the data input/outputto the external is carried out through the multiplexer for selecting aspecific bit line out of the plurality of bit lines BL and ZBL.Flip-flops are typically employed for the sense amplifier S/A, and apair of bit line signals are inputted as a differential signal. Thevoltage of a reference signal pairing with the bit line signal isgenerated by use of a dummy cell constituted by the same circuit as thatof the memory cell.

[0099] On reading, for example, after the bit line is charged at acertain potential, the word line WL is activated through a wordlinedriver. Then a signal charge stored in the capacitor including thecapacitor dielectric 31 interposed between the impurity region 4 andcell plate electrode 7 is read out to the bit line BL via the contact BC14, while a reference voltage is applied to the other, pairing bit lineZBL from the dummy cell. A voltage difference of the micro-signal basedon a difference between the bit line voltage which is read out from thecell data and the reference voltage is amplified by the sense amplifierS/A, and the resultant is transferred to an output circuit through themultiplexer.

[0100] On the other hand, on writing, the selected word line isactivated and the cell selection transistor is turned on or conducted. Ahigh or low potential level on the bit lines BL and ZBL is taken withinthe cell.

[0101] Next, a method of manufacturing a semiconductor integratedcircuit device in accordance with the embodiment 1 will be describedreferring to sectional process diagrams of FIG. 3.

[0102] In FIG. 3, reference numeral 30 designates a resist pattern; 31designates a gate oxide; 32 designates a doped polysilicon doped byphosphorus P and so on; and 33 and 33 a each designate a CVD oxide. Thesame other numerals as the above denote the same or corresponding partsand these redundant explanation will be omitted.

[0103] First, at Step ST1, after the device isolation region 3 is formedin a predetermined position on the substrate 1, p type well 2 is formedby an impurity implant with a high energy (FIG. 3A); at Step ST2, afterthe n type impurity region 4 for storing a signal charge of DRAMs isformed within the active region by the n+ ion implantation after theformation of the resist pattern 30 (FIG. 3B). At Step ST3, the gateoxide 31 having a thickness of 2-8 nm is formed on the p type well ofthe substrate 1, phosphorous P doped polysilicon with a thickness ofabout 10 nm is formed on the top, and further a CVD oxide 33 is formedwith a thickness of 10-15 nm to be stacked (FIG. 3C). At Step ST4, adesired resist pattern is created on the top, and the gate electrode 6and the cell plate electrode 7 of the memory cell transistor are formedthrough a certain etching process (FIG. 3D).

[0104] Subsequently, at Step ST5, an oxide is formed by a depositionwith 10 nm thick and subjected to anisotropic dry etching, thus formingthe sidewall 8 (FIG. 3E). At Step ST6, the n+ impurity region 10 isformed by an ion implantation. At Step ST7, the metal silicide film 12is formed on the p-type well 2, gate electrode 6 and cell plateelectrode 7 for a planar type capacitor of the substrate 1 (FIG. 3G).

[0105] Further, at Step ST8, the first interlayer dielectric 13 isformed on the top, and the contact holes 34 and 35 are formed throughphoto lithography and etching (FIG. 3H). At Step ST9, the first barriermetal layer 15 is deposited by sputtering and CVD-W is then depositedfor hole burying; these layers are subjected to blanket-etchback to formthe via plug 16; thereafter an aluminum deposition layer and anantireflection film are in turn formed by sputtering; the first aluminumwiring 17 is formed by a microfabrication including photolithography andetching while the first antireflection film 16 is prepared on the topsurface (FIG. 3I). Finally, at Step ST10, after the second interlayerdielectric 19 is formed on the top, the aluminum deposition layer andantireflection film are in turn formed similarly, and the secondaluminum wiring 21 with the second antireflection film 22 on the uppersurface is created by a microfabrication (FIG. 3J).

[0106] A desired semiconductor integrated circuit in accordance with theembodiment 1 may be obtained through the aforementioned process flow.

[0107] The layout placement of the memory according to the feature inaccordance with the embodiment 1 of the present invention will be nextdescribed.

[0108] As shown in FIG. 1, the memory cell in accordance with theembodiment 1 is configured by “closest packing cell placement”, whichmay be achieved as follows.

[0109] Namely, in the field placement, a memory cell array having aplurality of memory cells is created by the closest packing cellplacement when the memory cells are placed on the p-type well 2 of thep-type semiconductor substrate 1 with a predetermined pitch in therespective longitudinal and transverse directions to define the activearea and device isolation region 3.

[0110] Then, in the cell plate placement, a capacitor structure isprovided between a second conductive-type diffusion region formed in theactive area by an impurity implantation and the cell plate electrode CP7, which extends with the predetermined longitudinal size in thetransverse direction and which is formed so as to cover part of theactive area through the capacitor dielectric.

[0111] In addition, in the word line placement, the word line WL, whichis formed through the gate oxide 31, is arranged in the transversedirection of a vacancy or spacing of the active area which is not formedwith the cell plate electrode CP 7, and the gate electrode 6 of the MOStransistor is prepared on the active area.

[0112] The closest packing cell placement in a typical DRAM memory cellarray can take just an open-type bit line structure having a weak noiseresistance. However, as shown in FIG. 1, when the pitch in the row ortransverse direction (word line direction) is loosened to arrange twobit lines per pitch of a memory cell, the folded bit line arrangementstructure may be performed.

[0113] On the other hand, FIG. 4 is a layout diagram illustrating anarrangement which applies a memory cell to a half pitch cellconfiguration. In FIG. 4, reference symbol CL denotes a capacitor lossregion, the same other numerals above designate the same components orcorresponding parts, and their explanation will be omitted herein forbrevity. As shown in FIG. 4, when in accordance with the conventionalDRAM memory array, the word line WL and the cell plate CP electrode isformed by a common wiring layer, there occurs a wasteful region unusablefor capacitors or capacitor loss region CL.

[0114] The size ratio in length-to-width is typically almost 2:1 in thememory cell of conventional DRAMs, which employ a 8F2 cell of 2F inwidth size and 4F in length size, for example. Here, F is a value called“feature size” in design and is provided by adding a margin(registration in transcription processes and the like) to a design basis(=minimum dimension).

[0115] Referring to FIGS. 5 and 6, an optimum cell size will bedescribed based on the cell size calculation method of DRAM memory cellsin the embodiment 1.

[0116]FIGS. 5 and 6 are other illustrations of memory cellconfigurations: FIG. 5 corresponds to nx×ny F2 folded-BL mode, whileFIG. 6 corresponds to 6×15 F² folded-BL mode.

[0117] In FIGS. 5 and 6, reference symbols WL0-WL3 and BL0-BL5 denoteword lines in the transverse direction and bit lines in the longitudinaldirection, respectively. When the cell size in the transverse direction(word line direction) is symbolized by nxF and the cell size in thelongitudinal direction (bit line direction) by nyF, the area Scap of theplanar-type capacitor is provided by the following formula (1):

Scap=(nxF−F)·(nyF−naF−0.5F)  (1)

[0118] where na≧2.5, nx≧2, and ny≧4; both nx and ny are integers; Fdenotes minimum microfabrication dimension; Scap denotes capacitor areafor a signal.

[0119] In addition, the cell area Scell is provided by the followingformula (2):

Scell=nxF·nyF  (2)

[0120] From the above formulae (1) and (2), the na, nx, and ny valuesmay be introduced to minimize the cell area Scell.

[0121] The necessary condition to ensure a capacitor capacitance 25 fFrequired for a DRAM memory cell is searched for, for example, therespective conditions of the capacitor dielectric Tox=5 nm, 3.5 nm, and2 nm on a oxide basis when F=0.18 μm. The cell size calculation resultsof the corresponding DRAM memory cell are shown in tables of FIGS. 7-9(calculation values when na=2.5).

[0122] According to these, the following will be understood:

[0123] When Tox=5 nm, the minimum cell size can be achieved by 6.98 7μm² (width size=8F, length size=27F); when Tox=3.5 nm, the minimum cellsize by 3.62 7 μm² (width size=6F, length size=19F); when Tox=2 μm, theminimum cell size by 1.92 7 μm² (width size=5F, length size=12F).

[0124] As described above, according to the embodiment 1, since in thefield placement, the arrayed field patterns including the memory cellsare created through the closest packing manner, and the cell plateelectrodes CP 7 constructing the capacitor structure and the word lineserving as the gate electrode 6 are provided by the cell plate and wordline placements, respectively, the resultant memory cell may be laid outby the closest packing configuration which reduces extremely thecapacitor loss region. In such a way, the aspect ratio of the memorycell can be enlarged drastically as compared to the conventional DRAM,thereby achieving a DRAM memory cell having a memory size smallersufficiently than that of SRAMs.

[0125] In addition, in each memory of the field pattern in the fieldplacement, the pitch in the transverse direction is loosened, and thebit lines BL and ZBL arranged in the longitudinal direction are providedwith at least two lines every the pitch, thereby achieving a folded-typebit line configuration with a strong noise resistance.

[0126] Further, since the word line serving as the gate electrode 6 andthe cell plate electrode 7 are created by microfabrication of the wiringlayer formed through the same process step, the DRAM memory cell may beformed through the LOGIC processes with ease.

[0127] Embodiment 2

[0128]FIG. 10 is a schematic cross section of a semiconductor integratedcircuit device in accordance with an embodiment 2 of the presentinvention. In FIG. 10, reference numeral 40 designates a highly dopedimpurity region for increasing a coupling capacitance. The same othernumerals above designate the same components or corresponding parts andtheir explanation will be omitted herein for brevity, which is similarin the following.

[0129] In the semiconductor integrated circuit device of the embodiment2, there is a feature in that in the memory cell structure of theembodiment 1, the p+ highly doped impurity region 40 for increasing thecoupling capacitance is provided under an impurity region 4 for a planercapacitor. This achieves a memory cell having a Hi-C structure, what iscalled, and enlarges the capacitance of the node which stores data so asto prevent the data destruction within the memory cell due to softerrors.

[0130] Next, a method of manufacturing a semiconductor integratedcircuit device in accordance with the embodiment 2 will be describedwith reference to the sectional process flow diagram of FIG. 11. In thedrawing, reference numeral 30 designates a resist pattern; 31 designatesa gate oxide; 32 designates a p-doped polysilicon which is doped withphosphorous P; 33 and 33 a each designate a CVD oxide. The same othernumerals above designate the same components or corresponding parts andtheir explanation will be omitted.

[0131] First, at Step ST21, a device isolation region 3 is formed at apredetermined position on a semiconductor substrate 1, and then a p-typewell 2 is formed by a high-energy impurity implantation (FIG. 11A); atStep ST22, after formation of the resist pattern 30, the n-type impurityregion 4 and p+ impurity region 40 for storing a signal charge of a DRAMare formed in an active area by n+/p+ ion implants (FIG. 11B).

[0132] Then, at Step ST23, the gate oxide 31 is formed with a thicknessof 2-5 nm on the p-type well 2 in the substrate 1; the p-dopedpolysilicon 32 about 10 nm thick is formed on top; further, the CVDoxide 33 is formed and stacked with a thickness of 10-15 nm (FIG. 1C).On the top, at Step ST24, a desired resist pattern is created andetching process is implemented through the pattern, thus forming thegate electrode 6 and cell plate 7 of the memory cell transistor (FIG.3D).

[0133] However, subsequent steps are the same as those of the embodiment1, and these explanation will be omitted.

[0134] By way of the aforementioned process flow, a desiredsemiconductor integrated circuit device in accordance with theembodiment 2 will be obtained.

[0135] As described above, according to the embodiment 2, in the memorycell structure, the p+ highly doped impurity region 40 is created underthe impurity region 4 for the planar capacitor to increase the couplingcapacitance, thus achieving the Hi-C structure. In such a way, thesignal charge stored in the capacitor increases, thereby shrinking thecell size.

[0136] Embodiment 3

[0137]FIG. 12 illustrates a schematic cross section of a semiconductorintegrated circuit device in accordance with an embodiment 3 of thepresent invention, which illustrates the sectional structure of a PDRmemory cell. In FIG. 12, reference numeral 31 designates a gate oxidefor a MOS transistor; and 31 a designates a capacitor dielectric for asignal charge storage capacitor. Note that other components are the sameas the embodiment 1.

[0138] The semiconductor integrated circuit device of the embodiment 3has the following feature: In the memory cell structure, the thicknessof the capacitor dielectric 31 a for the signal charge storage capacitoris formed thinner than that of the gate oxide 31 for the MOS transistor;thus the area of the capacitor may be reduced and the storing amount ofthe charge may be enhanced.

[0139] Next, a method of manufacturing a semiconductor integratedcircuit device in accordance with the embodiment 3 will be describedwith reference to the sectional process flow diagram of FIG. 13.

[0140] First, at Step ST31, a device isolation region 3 is formed at apredetermined position on a substrate 1, and then a p-type well 2 isformed by an impurity implant with a high energy (FIG. 13A); at StepST32, a resist pattern 30 is formed, and then a n-type impurity region 4for storing a signal charge of a DRAM is formed in an active area by ann+ ion implant (FIG. 13B).

[0141] Then, at Step ST33, the gate oxide 31 is formed with a thicknessof 2-8 nm on a p-type well 2 of the substrate 1; a p-doped polysilicon32 is formed about 10 nm thick on top; further a CVD oxide 33 is formedand stacked thereon with a thickness of 10-15 nm (FIG. 13C). On top ofthis, at Step ST34, a desired resist pattern is formed and an etchingprocess is then carried out to the resultant for lithography, thusformeing a gate electrode 6 and a cell plate electrode 7 of a memorycell transistor (FIG. 13D).

[0142] However, subsequent steps are the same as those of the embodiment1 and these explanation will be omitted.

[0143] By way of the aforementioned process flow, a desiredsemiconductor integrated circuit device in accordance with theembodiment 3 will be obtained.

[0144] As described above, according to the embodiment 3, in the memorycell structure, the thickness of the capacitor dielectric 31 a is formedthinner than that of the gate oxide 31 for the MOS transistor, which mayreduce the capacitor area and enhance the charge amount thereof, therebyperforming the shrinkage of the cell size.

[0145] Embodiment 4

[0146]FIG. 14 illustrates a schematic cross section of a semiconductorintegrated circuit device in accordance with an embodiment 4 of thepresent invention, which illustrates the sectional structure of a PDRmemory cell. In FIG. 14, reference numeral 41 designates a trench-typecapacitor for a signal electric charge. Note that the other componentsare similar to those of the embodiments 1 and 3.

[0147] That is, the semiconductor integrated circuit device of theembodiment 4 has a feature that since the signal charge capacitor has atrench structure and trench-type capacitor in the memory cell structure,the cell size may be remarkably shrunk. Further, the thickness of thecapacitor dielectric 31 a is formed thinner than that of the gate oxide31 for MOS transistors, resulting in a synergy effect of shrinking thecapacitor area and enhancing the amount of storing the charge.

[0148] In this case, a manufacturing method of the semiconductorintegrated circuit device according to the embodiment 4 has the same asthat of the embodiment 1 except for adding only a step of creating thetrench structure after the formation of the p-type well 2 by etching tothe step ST1 of the embodiment 1, and thereby the explanation will beomitted.

[0149] As described above, since the embodiment 4 has the trench-typecapacitor structure and the thickness of the capacitor dielectric 31 ais formed thinner than that of the gate oxide 31 in the memory cellstructure, the capacitor area may be decreased and the charge storedamount may be enhanced, and further when the gate electrode 6 and thecell plate electrode 7 is formed through the same process, the DRAMmemory cell may be created with ease as well as the process for logiccircuits.

[0150] Embodiment 5

[0151]FIG. 15 illustrates a schematic cross section of a semiconductorintegrated circuit device in accordance with an embodiment 5 of thepresent invention, which illustrates the cross section of ap-channel-type PDRAM memory cell.

[0152] In FIG. 15, reference numeral 1 designates a semiconductorsubstrate; 2 b designates an n-type well (including a channel cut regionunder the isolation); 3 designates a device isolation region made of adielectric such as oxide; 4 b designates an impurity region for a planarcapacitor; 31 designates a gate oxide; 31 a designates a capacitordielectric; 6 b designates a gate electrode; 7 b designates a cell plateelectrode for the planar capacitor; 8 designates a dielectric forsidewalls; 9 designates a n-impurity region of a transistor; 10 bdesignates a p+ impurity region of the transistor; 11 designates a metalsalicide formed on the substrate 1; 12 designates a metal salicideformed on the gate electrode 6 b; 13 designates a first interlayerdielectric; 14 designates a bit line contact BC; 15 designates a firstbarrier metal layer; 16 designates a via plug made of CVD-W for holeburying; 17 designates a first aluminum wiring serving as bit lines BLand ZBL; 18 designates a first antireflection film for photolithography;19 designates a second interlayer dielectric; 20 designates a secondbarrier metal layer; 21 designates a second aluminum wiring; and 22designates a second antireflection film for photolithography.

[0153] Next, a method of manufacturing a semiconductor integratedcircuit device in accordance with the embodiment 5 will be describedwith reference to the sectional process flow diagrams of FIG. 16. In thedrawings, the reference numeral 30 designates a resist pattern; 31designates a gate oxide; 32 b designates a p-doped polysilicon dopedwith phosphorous P; and 33 and 33 a each designate a CVD oxide. The sameother numerals described above denote the same or corresponding partsand these explanation will be omitted.

[0154] First, at Step ST51, a device isolation region 3 is formed at apredetermined position on a substrate 1, and then a n-type well 2 b isformed by an impurity implant with a high energy (FIG. 16A); at StepST52, an impurity region 4 b for storing a signal charge for a DRAM isformed within an active region by a p+ ion implant after the formationof the resist pattern 30 (FIG. 16B).

[0155] Then, at Step ST53, the gate oxide 31 is formed with a thicknessof 2-8 nm on the n-type well 2 b of the substrate 1; a p-dopedpolysilicon 32 b is formed about 10 nm thick on top; further a CVD oxide33 is formed and stacked thereon with a thickness of 10-15 nm (FIG.16C). On top of this, at Step ST54, a desired resist pattern is formedand an etching process is then carried out through the pattern, thusforming a gate electrode 6 b and a cell plate electrode 7 b of a memorycell transistor (FIG. 16D).

[0156] Subsequently, at Step ST55, a gate oxide 10 nm thick is formedwith a deposition process, and sidewalls 8 are formed by anisotropic dryetching (FIG. 16E); at Step ST56, the p+ impurity region 10 b is createdby an ion implant (FIG. 16F); on top of this, at Step ST57, the metalsilicide is formed on the n-type well 2 b on the substrate 1 and on thegate electrode 6 b and cell plate electrode 7 b for the planar capacitor(FIG. 16G).

[0157] However, since subsequent steps conforms to ST8 to ST10 in FIG. 3in accordance with the embodiment 1, these explanation will be omitted.

[0158] By way of the aforementioned process flow, a desiredsemiconductor integrated circuit device in accordance with theembodiment 5 will be obtained.

[0159] As described above, according to the embodiment 5, the DRAMmemory cell having the planar-type capacitor maybe created through theCMOS logic process with ease.

[0160] In addition, since the layout of the memory cell may be arrangedin the closest packed cell configuration as well as the embodiment 1,the cell size can be made smaller. Further, when the aspect ratio ascompared to the conventional DRAM memory cell is enlarged greatly, thesize of the memory cell smaller sufficiently than that of SRAMs may beachieved.

[0161] Further, as in the embodiment 3, the thickness of the capacitordielectric 31 a is formed thinner than that of the gate oxide 31,thereby increasing the capacitor capacitance and making smaller the cellsize.

What is claimed is:
 1. A semiconductor integrated circuit devicecomprising: a field placement creating a field pattern in an array formby closest packing on a first conductance-type semiconductor substrate,said field pattern including a plurality of memory cells which define anactive area and a device isolation region of a field effect transistor,and which are arranged in a predetermined pitch in the longitudinal andtransverse directions, respectively, each memory cell having a patternof a certain length-to-width size; a cell plate placement providing acapacitor structure between a second conductance-type diffusion regionformed by an impurity implant to said active area and a cell plateelectrode formed so as to cover part of said active area with apredetermined cell plate pattern through a capacitor dielectric, saidcell plate pattern extending in said transverse direction with a certainlength size; and a word line placement in which a word line pattern isarranged in the transverse direction of a vacant zone of said activearea in which said cell plate electrode is not formed and serves as agate electrode of said field effect transistor on said active area, saidword line pattern being formed through a gate oxide at a predeterminedinterval, wherein the layout of a cell array of said memory cells isprovided by a closest packing cell configuration.
 2. The semiconductorintegrated circuit device according to claim 1, wherein the pitch of thememory cell in the transverse direction is loosened and at least two bitlines are arranged for each pitch of the memory cell in the longitudinaldirection.
 3. The semiconductor integrated circuit device according toclaim 1, wherein the thickness of the capacitor dielectric is the sameas that of the gate oxide.
 4. The semiconductor integrated circuitdevice according to claim 1, wherein the capacitor dielectric is madethinner than the gate oxide.
 5. The semiconductor integrated circuitdevice according to claim 1, wherein another first conductance-typediffusion having a highly doped diffusion region is provided under saiddiffusion region.
 6. The semiconductor integrated circuit deviceaccording to claim 1, wherein the capacitor structure has a trenchstructure.
 7. The semiconductor integrated circuit device according toclaim 1, wherein the first conductance-type is p-type and the secondconductance-type is n-type, or the first conductance-type is n-type andthe second conductance-type is p-type.
 8. A method of manufacturing asemiconductor integrated circuit device comprising: a first step offorming an active area and a device isolation region on the main surfaceof a semiconductor substrate and creating a field pattern of a memorycell array having a plurality of memory cells; a second step of carryingout an impurity implant on said main surface to form a first conductancetype well region which extends to a certain depth; a third step ofcreating a resist pattern which covers part of said active area to forma second conductance-type diffusion region by carrying out the impurityimplant through said resist pattern; a fourth step of forming in turn ainsulating film and an wiring layer each having a predeterminedthickness after removing said resist pattern; a fifth step of etchingsaid wiring layer through a desired pattern created on the top for amicrofabrication to form a gate electrode of a field effect transistorand a cell plate electrode; a sixth step of forming insulating sidewallsto said gate electrode and said cell plate to form a highly dopeddiffusion region with the second conductance-type through a high-doseion implant; a seventh step of forming a first interlayer dielectric toopen a contact hole therein by a microfabrication; and an eighth step offorming a metal wiring layer and creating a metal wiring from saidwiring layer through a microfabrication.
 9. The method of manufacturinga semiconductor integrated circuit device according to claim 8, whereinthe third step includes a step of forming a highly doped diffusionregion with the first conductance-type extending under said secondconductance-type diffusion region.
 10. The method of manufacturing asemiconductor integrated circuit device according to claim 8, whereinthe second step includes a step of forming another insulating film afterformation of said well region and the third step includes a step ofremoving said another insulating film after formation of said secondconductance-type diffusion region
 11. The method of manufacturing asemiconductor integrated circuit device according to claim 8, whereinthe first step includes a step of forming a trench within a section ofthe memory cell array.
 12. The method of manufacturing a semiconductorintegrated circuit device according to claim 8, wherein the firstconductance-type is p-type and the second conductance-type is n-type, orthe first conductance-type is n-type and the second conductance-type isp-type.
 13. A memory size calculation method of DRAM memory cellscharacterized in that a cell size of a planar-type capacitor in a memorycell laid out in accordance with a closest packing cell configuration isfound based on a minimum microfabrication dimension.
 14. A memory sizecalculation method for DRAM memory cells that when the cell sizes in thetransverse and longitudinal directions are represented nxF and nyF,respectively, based on a minimum microfabrication dimension F, and acapacitor area for a signal and a cell area are represented Scap andScell, respectively, respectively, and under the conditions of na≧2.5,nx≧2 (integer), and ny≧2 (integer), the na, nx, and ny values arederived so as to bring the cell area Scell to a minimum based on thefollowing formulae (1) and (2): Scap=(nxF−F)·(nyF−naF−0.5F)  (1)Scell=nxF·nyF  (2)